/*
  ******************************************************************************
  * @file    apt32f172.h
  * @author  APT AE Team
  * @version V1.13
  * @date    2019/08/01
  ******************************************************************************
  *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES 
  *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
  *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, 
  *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF 
  *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION 
  *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES 
  *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/ 
#ifndef _apt32f172_H
#define _apt32f172_H

/* Includes ------------------------------------------------------------------*/
#include "apt32f172_types_local.h"
#include "apt32f172_ck801.h"

/******************************************************************************/
/*                          IP registers structures                           */
/******************************************************************************/
/**
  * @brief  CPU Internal Structure
  */
typedef struct {
	volatile unsigned int ReservedA[4];		//0xE000E000
	volatile unsigned int CORET_CSR;			//0xE000E010
	volatile unsigned int CORET_RVR;			//0xE000E014
	volatile unsigned int CORET_CVR;			//0xE000E018
	volatile unsigned int ReservedB[57];		//0xE000E020
	volatile unsigned int ISER;				//0xE000E100
	volatile unsigned int ReservedC[15];		//
	volatile unsigned int IWER;				//0xE000E140
	volatile unsigned int ReservedD[15];		//
	volatile unsigned int ICER;				//0xE000E180
	volatile unsigned int ReservedE[15];		//
	volatile unsigned int IWDR;				//0xE000E1C0
	volatile unsigned int ReservedF[15];		//
	volatile unsigned int ISPR;				//0xE000E200
	volatile unsigned int ReservedG[31];		//
	volatile unsigned int ICPR;				//0xE000E280
	volatile unsigned int ReservedH[31];		//
	volatile unsigned int IABR;				//0xE000E300
	volatile unsigned int ReservedI[63];		//
	volatile unsigned int IPR[8];			//0xE000E400 ~ 0xE000E41C
	volatile unsigned int ReservedJ[504];	//
	volatile unsigned int ISR; 				//0xE000EC00
	volatile unsigned int IPTR; 				//0xE000EC04
}CSP_CK801_T;

/**
  * @brief  CMP Structure
  */
 typedef struct
 {
    CSP_REGISTER_T      CEDR;           /**< ID and Clock Control Register    */
    CSP_REGISTER_T      CR0;            /**< Control Register0                */
    CSP_REGISTER_T      CR1;            /**< Control Register1                */
    CSP_REGISTER_T      CR2;            /**< Control Register2                */
    CSP_REGISTER_T      CR3;            /**< Control Register3                */
    CSP_REGISTER_T      CR4;            /**< Control Register4                */
    CSP_REGISTER_T      FLTCR0;         /**< Filter Control Register0         */
    CSP_REGISTER_T      FLTCR1;         /**< Filter Control Register1         */
    CSP_REGISTER_T      FLTCR2;         /**< Filter Control Register2         */
    CSP_REGISTER_T      FLTCR3;         /**< Filter Control Register3         */
    CSP_REGISTER_T      FLTCR4;         /**< Filter Control Register4         */
    CSP_REGISTER_T      WCNT0;          /**< Capture Window Control Register0 */
    CSP_REGISTER_T      WCNT1;          /**< Capture Window Control Register1 */
    CSP_REGISTER_T      WCNT2;          /**< Capture Window Control Register2 */
    CSP_REGISTER_T      INPCR0;         /**< Input Config Register            */
    CSP_REGISTER_T      INPCR1;         /**< Input Config Register            */
    CSP_REGISTER_T      INPCR2;         /**< Input Config Register            */
    CSP_REGISTER_T      INPCR3;         /**< Input Config Register            */
    CSP_REGISTER_T      INPCR4;         /**< Input Config Register            */
    CSP_REGISTER_T      TRGCR;          /**< Trigger Config Register          */
    CSP_REGISTER_T      IMCR;           /**< Interrupt Masking Control Reg.   */
    CSP_REGISTER_T      RISR;           /**< Raw Interrupt Status Reg.        */
    CSP_REGISTER_T      MISR;           /**< Masked Interrupt Status Reg.     */
    CSP_REGISTER_T      ICR;            /**< Interrupt Clear Register         */
 } CSP_CMP_T, *CSP_CMP_PTR;

/**
  * @brief  EPWM Structure
  */

 typedef struct
 {
    CSP_REGISTER_T	CR;  		// 0x0000	Control
    CSP_REGISTER_T	LKCR;		// 0x0004	Link Mode Control
    CSP_REGISTER_T	LKTRG;		// 0x0008	Link Mode Trigger Control
    CSP_REGISTER_T	CNTR0;		// 0x000C	Counter Value
    CSP_REGISTER_T	CNTBR0;		// 0x0010	Counter Base Value
    CSP_REGISTER_T	PCNTR0;		// 0x0014	Pending Counter Value
    CSP_REGISTER_T	SLPCNTR0;	// 0x0018	Soft-lock Pending Counter Value
    CSP_REGISTER_T	CNTR1;		// 0x001C	Counter Value
    CSP_REGISTER_T	CNTBR1;		// 0x0020	Counter Base Value
    CSP_REGISTER_T	PCNTR1;		// 0x0024	Pending Counter Value
    CSP_REGISTER_T	SLPCNTR1;	// 0x0028	Soft-lock Pending Counter Value
    CSP_REGISTER_T	CNTR2;		// 0x002C	Counter Value
    CSP_REGISTER_T	CNTBR2;		// 0x0030	Counter Base Value
    CSP_REGISTER_T	PCNTR2;		// 0x0034	Pending Counter Value
    CSP_REGISTER_T	SLPCNTR2;	// 0x0038	Soft-lock Pending Counter Value
    CSP_REGISTER_T	CMPAR0;		// 0x003C	Compare Value A
    CSP_REGISTER_T	PCMPAR0;	// 0x0040	Pending Compare Value A
    CSP_REGISTER_T	SLPCMPAR0;	// 0x0044	Soft-lock Pending Compare Value A
    CSP_REGISTER_T	CMPBR0;		// 0x0048	Compare Value B
    CSP_REGISTER_T	PCMPBR0;	// 0x004C	Pending Compare Value B
    CSP_REGISTER_T	SLPCMPBR0;	// 0x0050	Soft-lock Pending Compare Value B
    CSP_REGISTER_T	CMPAR1;		// 0x0054	Compare Value A
    CSP_REGISTER_T	PCMPAR1;	// 0x0058	Pending Compare Value A
    CSP_REGISTER_T	SLPCMPAR1;	// 0x005C	Soft-lock Pending Compare Value A
    CSP_REGISTER_T	CMPBR1;		// 0x0060	Compare Value B
    CSP_REGISTER_T	PCMPBR1;	// 0x0064	Pending Compare Value B
    CSP_REGISTER_T	SLPCMPBR1;	// 0x0068	Soft-lock Pending Compare Value B
    CSP_REGISTER_T	CMPAR2;		// 0x006C	Compare Value A
    CSP_REGISTER_T	PCMPAR2;	// 0x0070	Pending Compare Value A
    CSP_REGISTER_T	SLPCMPAR2;	// 0x0074	Soft-lock Pending Compare Value A
    CSP_REGISTER_T	CMPBR2;		// 0x0078	Compare Value B
    CSP_REGISTER_T	PCMPBR2;	// 0x007C	Pending Compare Value B
    CSP_REGISTER_T	SLPCMPBR2;	// 0x0080	Soft-lock Pending Compare Value B
    CSP_REGISTER_T	WGCR0;		// 0x0084	Waveform Generator Engine Control
    CSP_REGISTER_T	WGCR1;		// 0x0088	Waveform Generator Engine Control
    CSP_REGISTER_T	WGCR2;		// 0x008C	Waveform Generator Engine Control
    CSP_REGISTER_T	OUTCR0;		// 0x0090	Output Control
    CSP_REGISTER_T	OUTCR1;		// 0x0094	Output Control
    CSP_REGISTER_T	OUTCR2;		// 0x0098	Output Control
    CSP_REGISTER_T	CFCR0; 		// 0x009C	Carrier Frequency Output Control
    CSP_REGISTER_T	CFCR1; 		// 0x00A0	Carrier Frequency Output Control
    CSP_REGISTER_T	CFCR2; 		// 0x00A4	Carrier Frequency Output Control
    CSP_REGISTER_T	EMR;  		// 0x00A8	Emergency Control
    CSP_REGISTER_T	SLCON; 		// 0x00AC	Emergency Control
    CSP_REGISTER_T	SLSTEP0;	// 0x00B0	Soft lock auto-dec/inc step Control
    CSP_REGISTER_T	SLSTEP1;	// 0x00B4	Soft lock auto-dec/inc step Control
    CSP_REGISTER_T  IER;        // 0x00B8       INT Enable/Disable Register
    CSP_REGISTER_T  ICR;        // 0x00BC       INT Pending Clear Register
    CSP_REGISTER_T  RISR;       // 0x00C0       INT Raw Status Register
    CSP_REGISTER_T  MISR;       // 0x00C4       INT Masked Status Register
    CSP_REGISTER_T  EXTRG0;     // 0x00C8       External Trigger Register
    CSP_REGISTER_T  EXTRG1;     // 0x00CC       External Trigger Register
 } CSP_EPWM_T, *CSP_EPWM_PTR;

/**
  * @brief  LED Structure
  */
 typedef struct
 {
    CSP_REGISTER_T      CR;             /**< Control Register                 */
    CSP_REGISTER_T      BRIGHT;         /**< Brightness Control Register      */
    CSP_REGISTER_T      RISR;           /**< Raw Interrupt Status Register    */
    CSP_REGISTER_T      IMCR;           /**< Interrupt Masking Control Reg.   */
    CSP_REGISTER_T      MISR;           /**< Masked Interrupt Status Register */
    CSP_REGISTER_T      ICR;            /**< Interrupt Clear Register         */
	CSP_REGISTER_T		RSVD;          
	CSP_REGISTER_T      TIMCR;          /**< Timing Control                   */
	CSP_REGISTER_T      BLKER;          /**< Blink enable Control             */
	CSP_REGISTER_T      BLKDR;          /**< Blink Clear Control              */
	CSP_REGISTER_T      BLKST;          /**< Blink Status Register            */
    CSP_REGISTER_T      SEGDATA0;       /**< Segment Data0                    */
    CSP_REGISTER_T      SEGDATA1;       /**< Segment Data1                    */
    CSP_REGISTER_T      SEGDATA2;       /**< Segment Data2                    */
    CSP_REGISTER_T      SEGDATA3;       /**< Segment Data3                    */
	CSP_REGISTER_T      SEGDATA4;       /**< Segment Data4                    */
    CSP_REGISTER_T      SEGDATA5;       /**< Segment Data5                    */
    CSP_REGISTER_T      SEGDATA6;       /**< Segment Data6                    */
	CSP_REGISTER_T      SEGDATA7;       /**< Segment Data7                    */
 } CSP_LED_T, *CSP_LED_PTR;

/**
  * @brief  OAMP Structure
  */
 typedef struct
 {
    CSP_REGISTER_T      CR0;            /**< OAMP0 Control Register                */
    CSP_REGISTER_T      CR1;            /**< OAMP1 Control Register                */
    CSP_REGISTER_T      GATR0;          /**< OAMP0 Gain tuning Register            */
    CSP_REGISTER_T      GATR1;          /**< OAMP1 Gain tuning Register            */
 } CSP_OAMP_T, *CSP_OAMP_PTR;

/**
  * @brief  SYSCON Structure
  */
typedef volatile struct {                            /*!< SYSCON Structure                         */
 volatile unsigned int IDCCR;                        /*!< Identification & System Controller Clock Control Register */
 volatile unsigned int GCER;                         /*!< System Controller General Control Enable Register */
 volatile unsigned int GCDR;                         /*!< System Controller General Control Disable Register */
 volatile unsigned int GCSR;                         /*!< System Controller General Control Status Register */
 volatile unsigned int _RSVD0;                       /*!< System Controller Power Control Enable Register */
 volatile unsigned int _RSVD1;                       /*!< System Controller Power Control Disable Register */
 volatile unsigned int _RSVD2;                       /*!< System Controller Power Control Status Register */
 volatile unsigned int SCLKCR;                       /*!< System Controller System Clock Selection & Division Register */
 volatile unsigned int PCLKCR;                       /*!< System Controller Peripheral Clock Selection & Division Register */
 volatile unsigned int _RSVD3;                       /*!< System Controller Peripheral Function Clock Selection & Division Register */
 volatile unsigned int PCER0;                        /*!< System Controller Peripheral Clock Enable Register */
 volatile unsigned int PCDR0;                        /*!< System Controller Peripheral Clock Disable Register */
 volatile unsigned int PCSR0;                        /*!< System Controller Peripheral Clock Status Register */
 volatile unsigned int PCER1;                        /*!< System Controller Peripheral Clock Enable Register */
 volatile unsigned int PCDR1;                        /*!< System Controller Peripheral Clock Disable Register */
 volatile unsigned int PCSR1;                        /*!< System Controller Peripheral Clock Status Register */
 volatile unsigned int OSTR;                         /*!< System Controller External OSC Stable Time Control Register */
 volatile unsigned int PSTR;                         /*!< System Controller PLL Stable Time Control Register */
 volatile unsigned int PLLCR;                        /*!< System Controller PLL PMS Value Control Register */
 volatile unsigned int LVDCR;                        /*!< System Controller LVD Control Register */
 volatile unsigned int CLCR;                         /*!< System Controller Internal OSC Fine Tune Register */
 volatile unsigned int PWRCR;                        /*!< System Controller Power Stable Time Control Register */
 volatile unsigned int OPT4;                         /*!< System Controller OSC Trim Control Register */
 volatile unsigned int OPT3;                         /*!< System Controller OSC Trim Control Register */
 volatile unsigned int OPT2;                         /*!< System Controller OSC Trim Control Register */
 volatile unsigned int OPT1;                         /*!< System Controller OSC Trim Control Register */
 volatile unsigned int OPT0;                         /*!< System Controller Protection Control Register */
 volatile unsigned int CQCR;                         /*!< System Controller Clock Quality Check Control Register */
 volatile unsigned int CQSR;                         /*!< System Controller Clock Quality Check Control Register */
 volatile unsigned int IECR;                         /*!< System Controller Interrupt Enable Register */
 volatile unsigned int IDCR;                         /*!< System Controller Interrupt Disable Register */
 volatile unsigned int IMSR;                         /*!< System Controller Interrupt Mask Register */
 volatile unsigned int IAR;                          /*!< System Controller Interrupt Active Register */
 volatile unsigned int ICR;                          /*!< System Controller Clear Status Register */
 volatile unsigned int RISR;                         /*!< System Controller Raw Interrupt Status Register */
 volatile unsigned int ISR;                          /*!< System Controller Raw Interrupt Status Register */
 volatile unsigned int RSR;                          /*!< System Controller Raw Interrupt Status Register */
 volatile unsigned int EXIRT;                        /*!< System Controller Reset Status Register */
 volatile unsigned int EXIFT;                        /*!< System Controller External Interrupt Mode 1 (Positive Edge) Register */
 volatile unsigned int EXIER;                        /*!< System Controller External Interrupt Mode 2 (Negative Edge) Register */
 volatile unsigned int EXIDR;                        /*!< System Controller External Interrupt Enable Register */
 volatile unsigned int EXIMR;                        /*!< System Controller External Interrupt Disable Register */
 volatile unsigned int EXIAR;                        /*!< System Controller External Interrupt Mask Register */
 volatile unsigned int EXICR;                        /*!< System Controller External Interrupt Active Register */
 volatile unsigned int EXIRS;                        /*!< System Controller External Interrupt Clear Status Register */
 volatile unsigned int IWDCR;                        /*!< System Controller Independent Watchdog Control Register */
 volatile unsigned int IWDCNT;                       /*!< System Controller Independent Watchdog Counter Value Register */
 volatile unsigned int IWDEDR;                       /*!< System Controller Independent Watchdog Enable/disable Register*/
 volatile unsigned int CINF0;                        /*!< Customer Information Content mirror of 1st byte*/
 volatile unsigned int CINF1;                        /*!< Customer Information Content mirror of 1st byte*/
 volatile unsigned int FINF0;                        /*!< Customer Information Content mirror of 1st byte*/
 volatile unsigned int FINF1;                        /*!< Customer Information Content mirror of 1st byte*/
 volatile unsigned int _RSVD6;                       /*! @0C4*/
 volatile unsigned int _RSVD7;                       /*! @0C8*/
 volatile unsigned int _RSVD8;                       /*! @0CC*/
 volatile unsigned int _RSVD9;                       /*! @0D0*/
 volatile unsigned int _RSVD10;                      /*! @0D4*/
 volatile unsigned int _RSVD11;                      /*! @0D8*/
 volatile unsigned int _RSVD12;                      /*! @0DC*/
 volatile unsigned int ERRINF;                       /*!< System Controller Context Save Register 0~3 */
 volatile unsigned int _RSVD13;                      /*! @0E4*/
 volatile unsigned int _RSVD14;                      /*! @0E8*/
 volatile unsigned int _RSVD15;                      /*! @0EC*/
 volatile unsigned int _RSVD16;                      /*! @0F0*/
 volatile unsigned int _RSVD17;                      /*! @0F4*/
 volatile unsigned int _RSVD18;                      /*! @0F8*/
 volatile unsigned int ACCENA;                       /*! Access Enable register for smart option area in syscon mirror*/
 volatile unsigned int PROT00;                       /*! Prot00*/
 volatile unsigned int PROT01;                       /*! Prot01*/
 volatile unsigned int PROT02;                       /*! Prot02*/
 volatile unsigned int PROT03;                       /*! Prot03*/
 volatile unsigned int PROT04;                       /*! Prot04*/
 volatile unsigned int PROT05;                       /*! Prot05*/
 volatile unsigned int PROT06;                       /*! Prot06*/
 volatile unsigned int PROT07;                       /*! Prot07*/
 volatile unsigned int PROT08;                       /*! Prot08*/
 volatile unsigned int PROT09;                       /*! Prot09*/
 volatile unsigned int PROT10;                       /*! Prot10*/
 volatile unsigned int PROT11;                       /*! Prot11*/
 volatile unsigned int PROT12;                       /*! Prot12*/
 volatile unsigned int PROT13;                       /*! Prot13*/
 volatile unsigned int PROT14;                       /*! Prot14*/
 volatile unsigned int PROT15;                       /*! Prot15*/
 volatile unsigned int PROT16;                       /*! Prot16*/
 volatile unsigned int PROT17;                       /*! Prot17*/
 volatile unsigned int PROT18;                       /*! Prot18*/
 volatile unsigned int PROT19;                       /*! Prot19*/
} CSP_SYSCON_T;

/**
  * @brief  TC0_GPT Structure
  */
/* Physical Timer Definition                                                 */
/** GPT one channel                                                          */
 #define GPT_ONE_CHANNEL    1u
/** GPT three channel                                                        */
 #define GPT_THREE_CHANNEL  3u

/**
*******************************************************************************
@brief GPT Channel Structure
*******************************************************************************
*/
 typedef volatile struct
 {
    volatile unsigned int  ReservedA[20];
    volatile unsigned int  ECR;               /**< Enable Clock Register            */
    volatile unsigned int  DCR;               /**< Disable Clock Register           */
    volatile unsigned int  PMSR;              /**< Power Management Status Register */
    volatile unsigned int  ReservedD;
    volatile unsigned int  CR;                /**< Control Register                 */
    volatile unsigned int  MR;                /**< Mode Register                    */
    volatile unsigned int  ReservedE;
    volatile unsigned int  CSR;               /**< Clear Status Register            */
    volatile unsigned int  SR;                /**< Status Register                  */
    volatile unsigned int  IER;               /**< Interrupt Enable Register        */
    volatile unsigned int  IDR;               /**< Interrupt Disable Register       */
    volatile unsigned int  IMR;               /**< Interrupt Mask Register          */
    volatile unsigned int  CV;                /**< Counter value Register           */
    volatile unsigned int  RA;                /**< Register A                       */
    volatile unsigned int  RB;                /**< Register B                       */
    volatile unsigned int  RC;                /**< Register C                       */
    volatile unsigned int  ReservedF[28];
 } CSP_GPT_T, *CSP_GPT_PTR;
 /**
*******************************************************************************
@brief GPT 1 Channel Structure
*******************************************************************************
*/
 typedef volatile struct
 {
    CSP_GPT_T      CHANNEL[GPT_ONE_CHANNEL];     /**< GPT Channel             */
 } CSP_GPT1C_T, *CSP_GPT1C_PTR;

/**
*******************************************************************************
@brief GPT 3 Channel Structure
*******************************************************************************
*/
 typedef volatile struct
 {
    CSP_GPT_T    CHANNEL[GPT_THREE_CHANNEL];   /**< GPT Channel             */
    volatile unsigned int BCR;                          /**< Block Control Register  */
    volatile unsigned int BMR;                          /**< Block Clock Mode Register */
 } CSP_GPT3C_T, *CSP_GPT3C_PTR;

/**
  * @brief  TC1_GTC Structure
  */
 typedef struct
 {
    CSP_REGISTER_T     	IDR;		/**< ID Register	              */
    CSP_REGISTER_T     	CSSR;        	/**< Clock Source Selection Register  */
    CSP_REGISTER_T     	CEDR;        	/**< Clock Enable/Disable Register    */
    CSP_REGISTER_T     	SRR;         	/**< Software Reset Register          */
    CSP_REGISTER_T     	CSR;        	/**< Control Set Register             */
    CSP_REGISTER_T     	CCR;        	/**< Control Clear Register           */
    CSP_REGISTER_T      SR;             /**< Status Register                  */
    CSP_REGISTER_T     	IMSCR;       	/**< Interrupt Mask Set/Clear Register*/
    CSP_REGISTER_T     	RISR;        	/**< Raw Interrupt Status Register    */
    CSP_REGISTER_T     	MISR;        	/**< Masked Interrupt Status Register */
    CSP_REGISTER_T    	ICR;        	/**< Interrupt Clear Register         */
    CSP_REGISTER_T     	CDR;        	/**< Clock Divider Register           */
    CSP_REGISTER_T     	CSMR;        	/**< Count Size Mask Register         */
    CSP_REGISTER_T      PRDR;           /**< Period Register                  */
    CSP_REGISTER_T      PULR;           /**< Pulse Register                   */
    CSP_REGISTER_T      RESVD[4];
    CSP_REGISTER_T      CUCR;           /**< Capture Up Count Register        */
    CSP_REGISTER_T      CDCR;           /**< Capture Down Count Register      */
    CSP_REGISTER_T      CVR;            /**< Counter Value Register           */
 } CSP_GTC_T, *CSP_GTC_PTR;

/**
  * @brief  TC2_ST16 Structure
  */
 typedef volatile struct 
 { 
    volatile unsigned int     IDR;            /**< IP ID-CODE Register              */
    volatile unsigned int     CEDR;           /**< Clock enable/disable register    */
    volatile unsigned int     RSSR;           /**< Software reset start stop        */
    volatile unsigned int     IMSCR;          /**< Interrupt mask set clear         */
    volatile unsigned int     RISR;           /**< Raw interrupt status             */
    volatile unsigned int     MISR;           /**< Masked interrupt status          */
    volatile unsigned int     ICR;            /**< Interrupt clear                  */
    volatile unsigned int     SR;             /**< Counter status                   */
    volatile unsigned int     ReservedA;       
    volatile unsigned int     MR;             /**< Mode                             */
    volatile unsigned int     ReservedB[2];  
    volatile unsigned int     CNTBR;          /**< Counter size base                */
    volatile unsigned int     CNTR;           /**< Counter value                    */
    volatile unsigned int     CDR;            /**< Clock divider                    */
    volatile unsigned int     ReservedC[5];  
    volatile unsigned int     PCNTR;          /**< Pending counter value            */
    volatile unsigned int     ReservedD[11];  
    volatile unsigned int     CRR;            /**< Channel enable/disable           */
    volatile unsigned int     CMR;            /**< Channel mode                     */
    volatile unsigned int     CIMSCR;         /**< Capture/compare interrupt en/dis */
    volatile unsigned int     CRISR;          /**< Capture/compare interrupt RISR   */
    volatile unsigned int     CMISR;          /**< Capture/compare interrupt MISR   */
    volatile unsigned int     CICR;           /**< Capture/compare interrupt clear  */
    volatile unsigned int     ReservedE;       
    volatile unsigned int     CAPSR;          /**< Latest capture status            */
    volatile unsigned int     ReservedF[8];  
    volatile unsigned int     CC0R;;          /**< Capture/compare register base    */
    volatile unsigned int     CC1R;;          /**< Capture/compare register base    */
 } CSP_ST16_T, *CSP_ST16_PTR;
 
/**
  * @brief  TC3_CTC Structure
  */
 typedef volatile struct 
 { 
    volatile unsigned int     IDR;            /**< IP ID-CODE Register                */
	volatile unsigned int     CSSR;           /**< Clock Source Selection Register    */
    volatile unsigned int     CEDR;           /**< Clock enable/disable register      */
    volatile unsigned int     SRR;            /**< Software reset register            */
    volatile unsigned int     CR;             /**< Control Register                   */
    volatile unsigned int     PRDR;           /**< Period Data Register               */
    volatile unsigned int     TIMDR;          /**< Timer Data Register                */
    volatile unsigned int     IMCR;           /**< Interrupt Masking Control Register */
	volatile unsigned int     RISR;           /**< Raw Interrupt Status Register      */
	volatile unsigned int     MISR;           /**< Masked Interrupt Status Register   */
    volatile unsigned int     ICR;            /**< Interrupt Clear Register           */
 } CSP_CTC_T, *CSP_CTC_PTR;

/**
  * @brief  adc Structure
  */
 typedef volatile struct
 {
    volatile unsigned int  ECR;              /**< Clock Enable Register             */
    volatile unsigned int  DCR;              /**< Clock Disable Register            */
    volatile unsigned int  PMSR;             /**< Power Management Status Register  */
    volatile unsigned int  ReservedB;
    volatile unsigned int  CR;               /**< Control Register                  */
    volatile unsigned int  MR;               /**< Mode Register                     */
    volatile unsigned int  ReservedC;
    volatile unsigned int  CSR;              /**< Clear Status Register             */
    volatile unsigned int  SR;               /**< Status Register                   */
    volatile unsigned int  IER;              /**< Interrupt Enable Register         */
    volatile unsigned int  IDR;              /**< Interrupt Disable Register        */
    volatile unsigned int  IMR;              /**< Interrupt Mask Register           */
    volatile unsigned int  SEQ[16];          /**< Conversion Mode Register 0~11     */
    volatile unsigned int  PRI;              /**< Conversion Priority Register      */
	volatile unsigned int  TDL0;				/**< ADC Trigger delay time 0          */
	volatile unsigned int  TDL1;				/**< ADC Trigger delay time 1          */
    volatile unsigned int  ReservedD[33];
    volatile unsigned int  DR[16];           /**< Convert Data Register             */
    volatile unsigned int  CMP0;             /**< Comparison Data Register             */
    volatile unsigned int  CMP1;             /**< Comparison Data Register             */
 } CSP_ADC12_T, *CSP_ADC12_PTR;

/**
  * @brief  GPIO Structure
  */
 typedef volatile struct
 {
    volatile unsigned int  CONLR;                /**< Control Low  Register                */
    volatile unsigned int  CONHR;                /**< Control High Register                */
    volatile unsigned int  WODR;                 /**< Write Output Data Register           */              
    volatile unsigned int  SODR;                 /**< Set Output Data (bit-wise) Register  */
    volatile unsigned int  CODR;                 /**< Clear Output Data (bit-wise) Register*/
    volatile unsigned int  ODSR;                 /**< Output Data Status Register          */
    volatile unsigned int  PSDR;                 /**< Pin Data Status Register             */
    volatile unsigned int  ReservedA;         
    volatile unsigned int  PUDR;                 /**< IO Pullup_Pulldown Register          */
    volatile unsigned int  DSCR;                 /**< Output Driving Strength Register     */
    volatile unsigned int  OMCR;                 /**< Slew-rate, Open-Drain Control        */
	volatile unsigned int  IECR;                	/**< EXI enable control                   */
    volatile unsigned int  IEER;	                /**< EXI bit enable control               */
	volatile unsigned int  IEDR;	                /**< EXI bit disable control              */
 } CSP_GPIO_T, *CSP_GPIO_PTR; 
 
  typedef volatile struct
 {
	volatile unsigned int  IGRPL;                	/**< EXI group control                   */
    volatile unsigned int  IGRPH;	                /**< EXI group control               */
 } CSP_IGRP_T, *CSP_IGRP_PTR; 
 
/**
  * @brief  I2C Structure
  */
 typedef volatile struct
 {
    volatile unsigned int  ReservedA[20];
    volatile unsigned int  ECR;           /* Enable Clock Register                  */
    volatile unsigned int  DCR;           /* Disable Clock Register                 */
    volatile unsigned int  PMSR;          /* Power Management Status Register       */
    volatile unsigned int  ReservedD;     
    volatile unsigned int  CR;            /* Control Register                       */
    volatile unsigned int  MR;            /* Mode Register                          */
    volatile unsigned int  ReservedE[2];
    volatile unsigned int  SR;            /* Status Register                        */
    volatile unsigned int  IER;           /* Interrupt Enable Register              */
    volatile unsigned int  IDR;           /* Interrupt Enable Register              */
    volatile unsigned int  IMR;           /* Interrupt Enable Register              */
    volatile unsigned int  DAT;           /* Serial Data Register                   */
    volatile unsigned int  ADR;           /* Serial Slave Address Register          */
    volatile unsigned int  THOLD;         /* Hold/Setup Delay Register              */
 } CSP_I2C_T, *CSP_I2C_PTR;

/**
  * @brief  IFC Structure
  */
typedef volatile struct {
        volatile unsigned int IDR ;
        volatile unsigned int CEDR ;
        volatile unsigned int SRR ;
        volatile unsigned int CMR ;
        volatile unsigned int CR ;
        volatile unsigned int MR ;
        volatile unsigned int PF_AR ;
        volatile unsigned int PF_DR ;
        volatile unsigned int KR ;
        volatile unsigned int ICR ;
        volatile unsigned int RISR ;
        volatile unsigned int MISR ;
        volatile unsigned int ICLR ;
} CSP_IFC_T ;

/**
  * @brief  SPI Structure
  */
typedef struct
{
	CSP_REGISTER_T  CR0;			/**< Control Register 0 */
	CSP_REGISTER_T  CR1;			/**< Control Register 1 */
	CSP_REGISTER_T  DR; 			/**< Receive FIFO(read) and transmit FIFO data register(write) */
	CSP_REGISTER_T  SR;			/**< Status register */
	CSP_REGISTER_T  CPSR;			/**< Clock prescale register */
	CSP_REGISTER_T  IMSCR;			/**< Interrupt mask set and clear register */
	CSP_REGISTER_T  RISR;			/**< Raw interrupt status register */
	CSP_REGISTER_T  MISR;			/**< Masked interrupt status register */
	CSP_REGISTER_T  ICR;			/**< Interrupt clear register */
} CSP_SSP_T, *CSP_SSP_PTR;

/**
  * @brief  Tkey Structure
  */
typedef volatile struct
{
   volatile unsigned int  TCH_CR0;               /* Control Register */
   volatile unsigned int  TCH_CR1;               /* Control Register */
   volatile unsigned int  TCH_HWPCR0;            /* HWP Control Register */
   volatile unsigned int  TCH_HWPCR1;            /* HWP Control Register */
   volatile unsigned int  TCH_BLFUCR;            /* Baseline Force Updating Control Register*/
   volatile unsigned int  TCH_BLFUDR;            /* Baseline Force Updating Value Register*/
   volatile unsigned int  TCH_START;             /* Start Register */
   volatile unsigned int  TCH_CEDR;              /* Touch Clock Enable/Disable Register */
   volatile unsigned int  TCH_CHDSTL;             /* Channel Disable Status Control Low Register */
   volatile unsigned int  TCH_CHDSTH;             /* Channel Disable Status Control High Register */
   volatile unsigned int  RSVDA[2];
   volatile unsigned int  TCH_CHCFG;             /* Touch Sensor Channel Configuration Register */
   volatile unsigned int  TCH_TSRL;               /* Touch Sensor Sensitivity Select Low Register */
   volatile unsigned int  TCH_TSRH;               /* Touch Sensor Sensitivity Select High Register */
   volatile unsigned int  TCH_GSR;               /* Touch Global Sensitivity Control Reg */
   volatile unsigned int  TCH_OSR0;             /* Offset Register for Channel 0 to 3 */
   volatile unsigned int  TCH_OSR1;             /* Offset Register for Channel 4 to 7 */
   volatile unsigned int  TCH_OSR2;             /* Offset Register for Channel 8 to 11 */
   volatile unsigned int  TCH_OSR3;             /* Offset Register for Channel 12 to 15 */
   volatile unsigned int  TCH_OSR4;             /* Offset Register for Channel 16 to 19 */
   volatile unsigned int  TCH_TKCRL;				/*Touch Key Interrupt Trigger Condition Low Register */
   volatile unsigned int  TCH_TKCRH;				/*Touch Key Interrupt Trigger Condition High Register */
   volatile unsigned int  TCH_RISR;             /* Raw Interrupt Status Register */
   volatile unsigned int  TCH_IMCR;             /* Interrupt Masking Control Register */
   volatile unsigned int  TCH_MISR;             /* Masked Interrupt Status Register */
   volatile unsigned int  TCH_ICR;              /* Interrupt Clear Register */
   volatile unsigned int  RSVDB;
   volatile unsigned int  TCH_CHxCNT[20];        /* Channel Counter Register */
   volatile unsigned int  RSVDC[4];
   volatile unsigned int  TCH_CHxBL[20];         /* Channel Baseline Register */
   volatile unsigned int  RSVDD[4];
   volatile unsigned int  TCH_TKEYST;            /* TKEY Status Register */
   volatile unsigned int  TCH_BLUPINF;           /* Baseline update channel information */
} CSP_TKEY_T, *CSP_TKEY_PTR; 

/**
  * @brief  UART Structure
  */
 typedef volatile struct
 {
    volatile unsigned int  DATA;               /**< Write and Read Data Register    */
    volatile unsigned int  SR;                 /**< Status Register                 */
    volatile unsigned int  CTRL;                /**< Control Register                */
    volatile unsigned int  ISR;                /**< Interrupt Status Register       */
    volatile unsigned int  BRDIV;               /**< Baud Rate Generator Register    */
    volatile unsigned int  ReservedA[20];
 } CSP_UART_T, *CSP_UART_PTR;

/**
  * @brief  USART Structure
  */
 typedef struct
 {
    CSP_REGISTER_T  IDR;				/**< ID Register	            */
    CSP_REGISTER_T  CEDR;               /**< Clock Enable/Disable Register  */
    CSP_REGISTER_T  SRR;                /**< Software Reset Register        */
    CSP_REGISTER_T  CR;                 /**< Control Register                */
    CSP_REGISTER_T  MR;                 /**< Mode Register                   */
    CSP_REGISTER_T  IMSCR;              /**< Interrupt Set/Clear Register       */
    CSP_REGISTER_T  RISR;               /**< Raw Interrupt Status Register      */
    CSP_REGISTER_T  MISR;               /**< Masked Interrupt Status Register   */
    CSP_REGISTER_T  ICR;                /**< Clear Status Register              */
    CSP_REGISTER_T  SR;                 /**< Status Register                 */
    CSP_REGISTER_T  RHR;                /**< Receiver Holding Register       */
    CSP_REGISTER_T  THR;                /**< Transmit Holding Register       */
    CSP_REGISTER_T  BRGR;               /**< Baud Rate Generator Register    */
    CSP_REGISTER_T  RTOR;               /**< Receiver Time-out Register      */
    CSP_REGISTER_T  TTGR;               /**< Transmitter Time-guard Register */
    CSP_REGISTER_T  LIR;                /**< LIN Identifier Register         */
    CSP_REGISTER_T  DFWR0;              /**< Data Field Write 0 Register     */
    CSP_REGISTER_T  DFWR1;              /**< Data Field Write 1 Register     */
    CSP_REGISTER_T  DFRR0;              /**< Data Field Read 0 Register      */
    CSP_REGISTER_T  DFRR1;              /**< Data Field Read 1 Register      */
    CSP_REGISTER_T  SBLR;               /**< Sync Break Length Register      */
    CSP_REGISTER_T  LCP1;               /**< Limit counter protocol 1        */
    CSP_REGISTER_T  LCP2;               /**< Limit counter protocol 2        */
 } CSP_USART_T, *CSP_USART_PTR;
 
 

 #define FLASHBase 0x00000000
 #define FLASHSize 0x00010000
 #define FLASHLimit (FLASHBase + FLASHSize) 
 #define DFLASHBase 0x10000000
 #define DFLASHSize 0x10001000
 #define DFLASHLimit (FLASHBase + FLASHSize) 

#ifdef REMAP
  #define SRAMBase 0x00000000
  #define SRAMSize 0x00000800
  #define SRAMLimit (SRAMBase + SRAMSize) 
  #define MEMVectorBase 0x00000700
  #define MEMVectorSize (0x50<<2)
#else
  #define SRAMBase 0x20000000
  #define SRAMSize 0x00001000
  #define SRAMLimit (SRAMBase + SRAMSize) 
  #define MEMVectorBase 0x20000F00
  #define MEMVectorSize (0x50<<2)
#endif

//--Peripheral Address Setting
#define APBPeriBase     0x40000000 

//--Each Peripheral Address Setting
#define APB_SFMBase     (APBPeriBase + 0x10000)
#define APB_IFCBase    	(APBPeriBase + 0x10000)
#define APB_SYSCONBase  (APBPeriBase + 0x11000)

#define APB_TKEYBase    (APBPeriBase + 0x20000)
#define APB_ADC0Base    (APBPeriBase + 0x30000)

#define APB_GPIOA0Base  (APBPeriBase + 0x40000) //A0  
#define APB_GPIOA1Base  (APBPeriBase + 0x40100) //A1 
#define APB_GPIOB0Base  (APBPeriBase + 0x41000) //B0 
#define APB_GPIOC0Base  (APBPeriBase + 0x42000) //C0 
#define APB_GPIOD0Base  (APBPeriBase + 0x43000) //D0 
#define APB_IGRPBase  	(APBPeriBase + 0x44000) //EXI GROUP CONTROL

#define APB_GPTBase    (APBPeriBase + 0x50000)
#define APB_GPTCH0Base    (APBPeriBase + 0x50000)
#define APB_GPTCH1Base    (APBPeriBase + 0x50100)
#define APB_GPTCH2Base    (APBPeriBase + 0x50200)
#define APB_GTCBase    (APBPeriBase + 0x51000)
#define APB_ST16Base   (APBPeriBase + 0x52000)
#define APB_CTCBase   (APBPeriBase + 0x53000)
#define APB_EPWMBase   (APBPeriBase + 0x54000)

#define APB_LED0Base    (APBPeriBase + 0x60000)
#define APB_CNTABase    (APBPeriBase + 0x70000)

#define APB_USART0Base   (APBPeriBase + 0x80000)
#define APB_UART1Base   (APBPeriBase + 0x81000)
#define APB_SPI0Base    (APBPeriBase + 0x90000)
#define APB_I2C0Base    (APBPeriBase + 0xA0000)
#define APB_CMPBase     (APBPeriBase + 0xB0000)
#define APB_OAMPBase     (APBPeriBase + 0xC0000)

#define APB_PCM_OPA_CMPBase    (APBPeriBase + 0xB0000)
#define APB_PCM_GPIOBase       (APBPeriBase + 0xB1000)
#define APB_PCM_PWMBase        (APBPeriBase + 0xB2000)
#define APB_PCM_INTCBase       (APBPeriBase + 0xB3000)


//--Interrupt Bit Position
#define CORET_INT   (0x01ul<<0)       //IRQ0
#define SYSCON_INT  (0x01ul<<1)       //IRQ1
#define IFC_INT     (0x01ul<<2)       //IRQ2
#define ADC_INT     (0x01ul<<3)       //IRQ3
#define TC0_0_INT   (0x01ul<<4)       //IRQ4
#define TC0_1_INT   (0x01ul<<5)       //IRQ5
#define TC0_2_INT   (0x01ul<<6)       //IRQ6
#define EXI0_INT    (0x01ul<<7)       //IRQ7
#define EXI1_INT    (0x01ul<<8)       //IRQ8
#define EPWM_INT    (0x01ul<<9)       //IRQ9
#define TC1_INT     (0x01ul<<10)      //IRQ10
#define TC2_INT     (0x01ul<<11)      //IRQ11
#define TC3_INT     (0x01ul<<12)      //IRQ12
#define USART0_INT   (0x01ul<<13)      //IRQ13
#define UART1_INT   (0x01ul<<14)      //IRQ14
#define DUMMY0      (0x01ul<<15)      //IRQ15
#define DUMMY1      (0x01ul<<16)      //IRQ16
#define I2C_INT     (0x01ul<<17)      //IRQ17
#define DUMMY2      (0x01ul<<18)      //IRQ18
#define SPI_INT     (0x01ul<<19)      //IRQ19
#define DUMMY3      (0x01ul<<20)      //IRQ20
#define EXI2_INT    (0x01ul<<21)      //IRQ21
#define EXI3_INT    (0x01ul<<22)      //IRQ22
#define EXI4_INT    (0x01ul<<23)      //IRQ23
#define DUMMY4      (0x01ul<<24)      //IRQ24
#define TKEY_INT    (0x01ul<<25)      //IRQ25
#define DUMMY5      (0x01ul<<26)      //IRQ26
#define LED_INT     (0x01ul<<27)      //IRQ27
#define CMP0_INT    (0x01ul<<28)      //IRQ28
#define CMP1_INT    (0x01ul<<29)      //IRQ29
#define DUMMYB      (0x01ul<<30)      //IRQ30
#define DUMMYC      (0x01ul<<31)      //IRQ31



extern CSP_CK801_T  *CK801     ;

extern CSP_IFC_T 	*IFC     ;
extern CSP_SYSCON_T *SYSCON   ;

extern CSP_TKEY_T 	*TKEY     ;
extern CSP_ADC12_T 	*ADC0     ;

extern CSP_GPIO_T 	*GPIOA0   ;
extern CSP_GPIO_T 	*GPIOA1   ;
extern CSP_GPIO_T 	*GPIOB0   ;
extern CSP_GPIO_T 	*GPIOC0   ;
extern CSP_GPIO_T 	*GPIOD0   ;
extern CSP_IGRP_T  	*EXIGRP   ;

extern CSP_GPT3C_T 	*GPT	  ;
extern CSP_GPT_T 	*GPTCH0	  ;
extern CSP_GPT_T 	*GPTCH1	  ;
extern CSP_GPT_T 	*GPTCH2	  ;

extern CSP_GTC_T 	*GTC	  ;
extern CSP_ST16_T 	*ST16	  ;
extern CSP_CTC_T 	*CTC	  ;
extern CSP_EPWM_T 	*EPWM	  ;

extern CSP_LED_T  	*LED0     ;

extern CSP_USART_T 	*USART0    ;
extern CSP_UART_T 	*UART1    ;
extern CSP_SSP_T  	*SPI0     ;
extern CSP_I2C_T  	*I2C0     ;
extern CSP_CMP_T  	*CMP      ;
extern CSP_OAMP_T  	*OAMP     ;


//ISR Define for generating special interrupt related ASM (CK801), with compile option -mistack
void MisalignedHandler(void) __attribute__((isr));
void IllegalInstrHandler(void) __attribute__((isr));
void AccessErrHandler(void) __attribute__((isr));
void BreakPointHandler(void) __attribute__((isr));
void UnrecExecpHandler(void) __attribute__((isr));
void Trap0Handler(void) __attribute__((isr));
void Trap1Handler(void) __attribute__((isr));
void Trap2Handler(void) __attribute__((isr));
void Trap3Handler(void) __attribute__((isr));
void CORETHandler(void) __attribute__((isr));
void PendTrapHandler(void) __attribute__((isr));
void SYSCONIntHandler(void) __attribute__((isr));
void IFCIntHandler(void) __attribute__((isr));
void EXI0IntHandler(void) __attribute__((isr));
void EXI1IntHandler(void) __attribute__((isr));
void EXI2to3IntHandler(void) __attribute__((isr));
void EXI4to9IntHandler(void) __attribute__((isr));
void EXI10to15IntHandler(void) __attribute__((isr));
void CNTAIntHandler(void) __attribute__((isr));
void USART0IntHandler(void) __attribute__((isr));
void UART1IntHandler(void) __attribute__((isr));
void I2CIntHandler(void) __attribute__((isr));
void GPT_0IntHandler(void) __attribute__((isr));
void GPT_1IntHandler(void) __attribute__((isr));
void GPT_2IntHandler(void) __attribute__((isr));
void GTCIntHandler(void) __attribute__((isr));
void STC16IntHandler(void) __attribute__((isr));
void CTCIntHandler(void) __attribute__((isr));
void ADCIntHandler(void) __attribute__((isr));
void LEDIntHandler(void) __attribute__((isr));
void TKEYIntHandler(void) __attribute__((isr));
void SPIIntHandler(void) __attribute__((isr));
void CMP0IntHandler(void) __attribute__((isr));
void CMP1IntHandler(void) __attribute__((isr));
void EPWMIntHandler(void) __attribute__((isr));

/*****************************************************************************
************************** Timer delay ***************************************
******************************************************************************/

extern	void delay_nms(unsigned int t);

/* ##########################   NVIC functions  #################################### */


/**
 * @brief  Enable Interrupt in NVIC Interrupt Controller
 *
 * @param  IRQn   The positive number of the external interrupt to enable
 *
 * Enable a device specific interupt in the NVIC interrupt controller.
 * The interrupt number cannot be a negative value.
 */


/**
 * @brief  Disable the interrupt line for external interrupt specified
 * 
 * @param  IRQn   The positive number of the external interrupt to disable
 * 
 * Disable a device specific interupt in the NVIC interrupt controller.
 * The interrupt number cannot be a negative value.
 */
__INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
        CK801->ICER = 1 << (uint32_t)(IRQn);
}

/**
 * @brief  Read the interrupt pending bit for a device specific interrupt source
 * 
 * @param  IRQn    The number of the device specifc interrupt
 * @return         always 0
 */
__INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
        return (uint32_t)(CK801->ISPR);
}

/**
 * @brief  Set the pending bit for an external interrupt
 * 
 * @param  IRQn    The number of the interrupt for set pending
 *
 * No effect.
 */
__INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
	CK801->ISPR = (1 << (uint32_t)(IRQn));
}
/**
 * @brief  Clear the pending bit for an external interrupt
 *
 * @param  IRQn    The number of the interrupt for clear pending
 *
 * No effect.
 */
__INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
	CK801->ICPR = (1 << (uint32_t)(IRQn));
}

/**
 * @brief  Read the active bit for an external interrupt
 *
 * @return         always 0
 *
 */
__INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
    return (CK801->IABR & (1 << IRQn));
}

__INLINE uint32_t NVIC_GetActiveVector(void)
{
	unsigned int vectactive = 0;
	//isr low 8bits gives the active vector
	vectactive = (CK801 ->ISR & 0xff);
    return vectactive;
}

/**
 * @brief  Set the priority for an interrupt
 *
 * @param  IRQn      The number of the interrupt for set priority
 * @param  priority  The priority to set ,the number rang: [0-3]
 *
 * Set the priority for the specified interrupt. The interrupt 
 * number must be positive to specify an external (device specific) 
 * interrupt.
 */
__INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{

	uint32_t tmp = ((IRQn & 0x03) << 3);
	uint8_t index = IRQn>>2;
    if(IRQn >= 0) {
    	CK801->IPR[index] &= ~(0xff << tmp);
    	CK801->IPR[index] |= priority << (tmp+6);
    }

}
/**
 * @brief  Read the priority for an interrupt
 *
 * @param  IRQn      The number of the interrupt for get priority
 * @return           The priority for the interrupt
 *
 * Read the priority for the specified interrupt. The interrupt 
 * number must be positive to specify an external (device specific) 
 * interrupt.
 */
__INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
	uint32_t tmp = ((IRQn & 0x03) << 3);
	uint8_t index = IRQn>>2;
	return (uint32_t)(CK801->IPR[index])>>(tmp + 6);
}


/*###################################################################*/
/*#############    Threshold Enable & Set Threshold   ###############*/
/*###################################################################*/

/************************************************************
 * @brief	enable NVIC threshold
 * @name: NVIC_EnableThreshold
 * @no param
 *
 */

__INLINE void NVIC_EnableThreshold(void)
{
	CK801 ->IPTR |= 0x80000000;
}

/************************************************************
 * @brief	disnable NVIC threshold
 * @name: NVIC_DisableThreshold
 * @no param
 *
 */

__INLINE void NVIC_DisableThreshold(void)
{
	CK801 ->IPTR &= ~0x80000000;
}


/************************************************************
 * @brief	set NVIC Priothreshold
 * @name: NVIC_SetPrioThreshold
 * @param prioshreshold		the priority of threshold[0,3]
 *
 */

__INLINE void NVIC_SetPrioThreshold(uint8_t prioshreshold)
{
	CK801 -> IPTR &= 0xffffff00;
	CK801 -> IPTR |= (prioshreshold << 6);
}

/************************************************************
 * @brief	set NVIC Vectthreshold
 * @name: NVIC_SetVectThreshold
 * @param vectthreshold		the vector of threshold[0,31]
 *
 */

__INLINE void NVIC_SetVectThreshold(uint8_t vectthreshold)
{
	CK801 -> IPTR &= 0xffff00ff;
	CK801 -> IPTR |= ((vectthreshold + 32) << 8);
}


/*###################################################################*/
/*################    Low Power Wakeup Enable     ###################*/
/*###################################################################*/

/*************************************************************
 * @name:	NVIC_PowerWakeUp_Enable
 * @brief:	enable the bit for Power wake up
 * @param:	irqn	the irqnumber,eg:CK802_CORETIM_IRQn
 */
__INLINE void NVIC_PowerWakeUp_Enable(IRQn_Type irqn)
{
	CK801->IWER |= (1 << irqn);
}

/*************************************************************
 * @name:	NVIC_PowerWakeUp_Disable
 * @func:	disable the bit for Power wake up
 * @param:	irqn	the irqnumber,eg:CK802_CORETIM_IRQn
 */
__INLINE void NVIC_PowerWakeUp_Disable(IRQn_Type irqn)
{
	CK801->IWDR |= (1 << irqn);
}

/*************************************************************
 * @name:	NVIC_PowerWakeUp_EnableAll
 * @func:	enable all bits for Power wake up
 * @param:	none
 */
__INLINE void NVIC_PowerWakeUp_EnableAll(void)
{
	CK801->IWER = 0xffffffff;
}

/*************************************************************
 * @name:	NVIC_PowerWakeUp_EnableAll
 * @func:	disable all bits for Power wake up
 * @param:	none
 */
__INLINE void NVIC_PowerWakeUp_DisableAll(void)
{
	CK801->IWDR = 0xffffffff;
}

/* ##########################   NVIC functions  #################################### */

#endif   /**< apt32f172_H */

/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/